1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method for making a semiconductor device having a sacrificial salicidation layer that assists in reducing junction consumption during salicidation.
2. Descripton of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor, e.g., channel length, junction depths, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size or scale of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. However, the reduction in the channel length also requires a reduction in the depth of the source and drain regions adjacent the gate conductor.
Another operation that is performed on traditional semiconductor devices is known as salicidation. In general, salicidation involves the process of forming a layer of metal, e.g., titanium, above the gate conductor and source/drain regions of a transistor device, and, thereafter, subjecting the device to a heat treatment process such that a metal silicide, e.g., titanium silicide, is formed where the titanium is exposed to polysilicon. The purpose of the salicidation process is to, among other things, reduce the resistance of the components subject to the salicidation process. However, the traditional salicidation process has become problematic with modern semiconductor devices that have shallow source/drain junctions, e.g., junction depths on the order of 1000 .ANG. or less. In particular, during such salicidation processes, some of the existing source/drain regions are consumed. Typically, this consumption may be on the order of twice the thickness of the metal silicide. Such consumption acts to reduce the dopant present in the source/drain regions and adversely impacts the electrical performance characteristics of the source/drain regions, and ultimately, the performance of the semiconductor device. Given the fact that source/drain regions in modern semiconductor devices are already made very shallow, further reductions in these regions during the salicidation process is undesirable.
The present invention is directed to a semiconductor device that minimizes or reduces some or all of the aforementioned problems and a method of making same.